Name
Title | ||
|---|---|---|
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture |
Abstract | ||
|---|---|---|
This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network (NoC). Concurrent BIST operations are carried out after reset at each switch, thus resulting in scalable test application time with network size. The key principle consists of exploiting the inherent structural redundancy of the NoC architecture in a cooperative way, thus detecting faults in test pattern generators too. At-speed testing of stuck-at faults can be performed in less than 1200 cycles regardless of their size, with an hardware overhead of less than 11%. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/DATE.2011.5763109 | Design, Automation & Test in Europe Conference & Exhibition |
Keywords | Field | DocType |
built-in self test,network-on-chip,NoC architecture,at-speed testing,built-in self-test architecture,concurrent BIST operations,network size,network-on-chip,scalable test application time,self-diagnosis procedure,structural redundancy,stuck-at faults,test pattern generators | Network size,Architecture,Computer science,Parallel computing,Network on a chip,Communication channel,Real-time computing,Redundancy (engineering),Multiplexing,Built-in self-test,Scalability | Conference |
ISSN | ISBN | Citations |
1530-1591 | 978-1-61284-208-0 | 25 |
PageRank | References | Authors |
0.83 | 19 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Strano, A. | 1 | 25 | 0.83 |
| Gómez, C. | 2 | 27 | 1.26 |
| Ludovici, D. | 3 | 34 | 1.40 |
| Favalli, M. | 4 | 25 | 0.83 |