Name
Abstract | ||
|---|---|---|
This paper presents a block-serial fully-overlapped Quasi-Cyclic Low Density Parity Check (QC-LDPC) decoder for IEEE 802.11n. Based on the circuit retiming and message bypassing techniques, this decoder effectively improved the previous work proposed by Xiang et al. with an 11% clock-rate increase and a 3% decoding time reduction on average. Moreover, the proposed chip spends about 3.67 mm in 90 nm CMOS technology, its power approximately consumes 171 mW at 250 MHz, and throughput of the proposed design can reach 672 Mbps. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ICCE.2014.6776079 | ICCE |
Keywords | Field | DocType |
cmos integrated circuits,block codes,cyclic codes,decoding,parity check codes,wireless lan,cmos technology,ieee 802.11,bit rate 672 mbit/s,block-serial fully-overlapped qc-ldpc decoder,circuit retiming,frequency 250 mhz,message bypassing techniques,power 171 mw,quasi-cyclic low density parity check decoder,size 90 nm | Retiming,Low-density parity-check code,Computer science,Block code,Chip,Electronic engineering,CMOS,IEEE 802,Soft-decision decoder,Decoding methods | Conference |
ISSN | ISBN | Citations |
2158-3994 | 978-1-4799-1290-2 | 2 |
PageRank | References | Authors |
0.37 | 3 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chu Yu | 1 | 3 | 2.42 |
| hosheng chuang | 2 | 2 | 0.37 |
| Bor-Shing Lin | 3 | 94 | 16.30 |
| P. H. Cheng | 4 | 55 | 13.08 |
| Sao-Jie Chen | 5 | 523 | 62.97 |