Paper Info
Title
A 12 Gb/s standard cell based ECL 4:1 serializer with asynchronous parallel interface
Abstract
This paper presents an implementation of an high speed, double data rate, fully differential ECL (Emitter Coupled Logic) serializer. For this purpose, a novel robust ECL standard cell library was developed. The design is composed using a digital design flow, described in Hardware Description Language (HDL), and transfered manually in the analog design environment. The serializer has a parallel 4-bit FIFO interface, and can either communicate synchronously or asynchronously using the 2-phase bundled-data protocol. The FIFO consists of 4 stages and is realized as a micropipeline with a Muller pipeline as backbone. The entire circuit is developed in a 0.25 μm SiGe BiCMOS process and operates nominally at 3.3V. Simulation results show a maximal data rate of 12 Gb/s while drawing a current of 96.64mA only. Finally, the design and its components are compared to other SiGe-based published implementations.
Year
DOI
Venue
2013
10.1109/ICECS.2013.6815330
Electronics, Circuits, and Systems
Keywords
Field
DocType
BiCMOS logic circuits,Ge-Si alloys,cellular arrays,emitter-coupled logic,hardware description languages,BiCMOS process,ECL standard cell library,HDL,Muller pipeline,SiGe,asynchronous parallel interface,bit rate 12 Gbit/s,bundled-data protocol,current 96.64 mA,digital design flow,emitter coupled logic serializer,fully differential ECL,hardware description language,micropipeline,parallel 4-bit FIFO interface,size 0.25 mum,voltage 3.3 V,CML,ECL,Emitter Coupled Logic,MUX,Micropipelines,SerDes,Serializer
FIFO (computing and electronics),Computer science,Emitter-coupled logic,Design flow,Serializer,Electronic engineering,Standard cell,Parallel port,Double data rate,Hardware description language,Embedded system
Conference
Citations 
PageRank 
References 
1
0.45
3
Authors
4
Name
Order
Citations
PageRank
Oliver Schrape1199.55
Markus Appel210.45
Frank Winkler3369.50
Milos Krstic417039.42