Name
Abstract | ||
|---|---|---|
A speed-enhanced 10-b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented with a straightforward DAC switching algorithm. The capacitor DAC is virtually divided into three sub-DACs for ADEC with negligible hardware overhead. The redundant decision cycles between stages reconfigure the capacitor connection of the DAC. These redundancies guarantee 10-b linearity under 4-b-accurate DAC settling in the MSB decision and the optimally designed ADC enhances the conversion speed by 37%. A prototype ADC was implemented in a CMOS 0.13-μm technology. The chip consumes 550 μW and achieves a 50.6-dB SNDR at 40 MS/s under a 1.2-V supply. The figure-of-merit (FOM) is 50 fJ/conversion-step. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/JSSC.2011.2151450 | Solid-State Circuits, IEEE Journal of |
Keywords | Field | DocType |
CMOS integrated circuits,analogue-digital conversion,capacitors,digital-analogue conversion,error correction,redundancy,CMOS technology,DAC switching algorithm,MSB decision,multistep addition only digital error correction,power 550 muW,redundant decision cycle,size 0.13 mum,speed enhanced asynchronous SAR ADC,voltage 1.2 V,word length 10 bit,Addition-only digital error correction (ADEC),SAR ADC,asynchronous,digital error correction,multistep binary error correction | Asynchronous communication,Computer science,Linearity,CMOS,Electronic engineering,Chip,Error detection and correction,Redundancy (engineering),Successive approximation ADC,Least significant bit | Journal |
Volume | Issue | ISSN |
46 | 8 | 0018-9200 |
ISBN | Citations | PageRank |
978-1-4244-5758-8 | 10 | 1.06 |
References | Authors | |
8 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sang-Hyun Cho | 1 | 143 | 21.38 |
| Chang-Kyo Lee | 2 | 28 | 4.02 |
| Jong-Kee Kwon | 3 | 158 | 23.10 |
| Seung-Tak Ryu | 4 | 299 | 46.61 |