Name
Abstract | ||
|---|---|---|
Although communication fabrics at the microarchitectural level are mainly composed of standard primitives such as queues and arbiters, to get an executable model one has to connect these primitives with glue logic to complete the description. In this paper we identify a richer set of microarchitectural primitives that allows us to describe complete systems by composition alone. This enables us to build models faster (since models are now simply wiring diagrams at an appropriate level of abstraction) and to avoid common modeling errors such as inadvertent loss of data due to incorrect timing assumptions. Our models are formal and they are used for model checking as well as dynamic validation and performance modeling. However, unlike other formalisms this approach leads to a precise yet intuitive graphical notation for microarchitecture that captures timing and functionality in sufficient detail to be useful for reasoning about correctness and for communicating microarchitectural ideas to RTL and circuit designers and validators. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/MDT.2011.72 | IEEE Design & Test of Computers |
Keywords | Field | DocType |
B Hardware,B.1.4.e Verification,B.4.3.f Topology,B.6.2 Reliability and Testing,B.7.2.e Verification,C.0.d Modeling of computer architecture,C.0.e System architectures,C.1 Processor Architectures,C.3.d Real-time and embedded systems,integration and modeling | Notation,Programming language,Model checking,Computer science,Correctness,Glue logic,Rotation formalisms in three dimensions,Executable,Microarchitecture,Formal verification | Journal |
Volume | Issue | ISSN |
PP | 99 | 2168-2356 |
Citations | PageRank | References |
17 | 0.71 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Satrajit Chatterjee | 1 | 258 | 15.65 |
| Michael Kishinevsky | 2 | 814 | 67.81 |
| Ümit Y. Ogras | 3 | 203 | 15.03 |