Name
Title | ||
|---|---|---|
A Parallel Hardware Architecture for Real-Time Object Detection with Support Vector Machines |
Abstract | ||
|---|---|---|
Object detection applications are often associated with real-time performance constraints that stem from the embedded environment that they are often deployed in. Consequently, researchers have proposed dedicated hardware architectures, utilizing a variety of classification algorithms targeting object detection. Support Vector Machines (SVMs) is among the most popular classification algorithms used in object detection yielding high accuracy rates. However, existing SVM hardware implementations attempting to speed up SVM classification, have either targeted only simple applications, or SVM training. As such, there are limited proposed hardware architectures that are generic enough to be used in a variety of object detection applications. Hence, this paper presents a parallel array architecture for SVM-based object detection, in an attempt to show the advantages, and performance benefits that stem from a dedicated hardware solution. The proposed hardware architecture provides parallel processing, resource sharing among the processing units, and efficient memory management. Furthermore, the size of the array is scalable to the hardware demands, and can also handle a variety of applications such as multiclass classification problems. A prototype of the proposed architecture was implemented on an FPGA platform and evaluated using three popular detection applications, demonstrating real-time performance (40-122 fps for a variety of applications). |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TC.2011.113 | Computers, IEEE Transactions |
Keywords | Field | DocType |
field programmable gate arrays,object detection,parallel architectures,resource allocation,storage management,support vector machines,FPGA platform,SVM classification,SVM hardware implementations,SVM training,embedded environment,memory management,multiclass classification problems,parallel array architecture,parallel hardware architecture,parallel processing,real-time object detection,real-time performance constraints,resource sharing,support vector machines,Field programmable gate array (FPGA),object detection,parallel architecture.,support vector machines | Object detection,Computer science,Parallel computing,Support vector machine,Field-programmable gate array,Real-time computing,Statistical classification,Speedup,Hardware architecture,Multiclass classification,Scalability | Journal |
Volume | Issue | ISSN |
61 | 6 | 0018-9340 |
Citations | PageRank | References |
24 | 1.15 | 25 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christos Kyrkou | 1 | 102 | 14.05 |
| Theocharis Theocharides | 2 | 205 | 26.83 |