Title
FPGA implementation of multiple hardware watchdog timers for enhancing real-time systems security
Abstract
In this work, we deal with securing the real-time systems by providing them with additional hardware watchdog timers. This paper proposes the basic concept of the multiple hardware watchdog timers system and describes the proposed architecture of the system providing 256 hardware watchdog timers. It deals with the particular implementation of the system in the FPGA programmable device. The results show that the developed system has a promising potential for enhancing the security of real-time systems and that the proposed architecture is suitable to be implemented in reasonably small programmable devices.
Year
DOI
Venue
2011
10.1109/EUROCON.2011.5929215
EUROCON - International Conference Computer as a Tool
Keywords
Field
DocType
field programmable gate arrays,real-time systems,FPGA,multiple hardware watchdog timers,programmable device,real-time systems,security,FPGA,real-time systems,watchdog timer
Architecture,Synchronization,Computer science,Field-programmable gate array,Real-time computing,Watchdog timer,Computer hardware,Embedded system,Encoding (memory)
Conference
ISBN
Citations 
PageRank 
978-1-4244-7486-8
1
0.40
References 
Authors
0
2
Name
Order
Citations
PageRank
Maria Pohronska110.40
Tibor Krajcovic282.18