Name
Abstract | ||
|---|---|---|
A novel spike-based computation architecture has been developed which represents synaptic weights in time. An analog chip with 32 neurons, 1024 synapses and an AER block has been fabricated in 0.5μm technology. A digital implementation of the architecture having 6,144 neurons and 100,352 synapses on an FPGA is also described. A digital controller for routing spikes can processes up to 34 million synapses per second. The architecture is called the time machine as it operates on timing events and uses time to store weights. The time machine is general enough for implementing many spike-based algorithms yet provides flexibility and configurability. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISCAS.2011.5937658 | Circuits and Systems |
Keywords | Field | DocType |
field programmable gate arrays,logic design,neural chips,AER block,FPGA,analog chip,digital controller,routing spikes,size 0.5 mum,spike-based algorithms,spike-based computation architecture,synaptic weights,time machine | Logic synthesis,Architecture,Computer science,Analog chip,Field-programmable gate array,Electronic engineering,Digital control,Computation | Conference |
ISSN | ISBN | Citations |
0271-4302 E-ISBN : 978-1-4244-9472-9 | 978-1-4244-9472-9 | 4 |
PageRank | References | Authors |
0.42 | 6 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vaibhav Garg | 1 | 96 | 9.58 |
| Ravi Shekhar | 2 | 34 | 3.82 |
| John G. Harris | 3 | 413 | 75.11 |