Name
Title | ||
|---|---|---|
Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling |
Abstract | ||
|---|---|---|
This study aims to understand the potential of buried Silicon-Germanium (SiGe) technology from the perspective of VLSI logic circuits exploiting aggressive dynamic voltage scaling. Appropriate circuit- and system-level metrics are extracted from wafer-level measurements on 45nm SiGe pMOSFETs with a high-k/metal gate stack and systematically benchmarked to Si channel devices. The comparative analysis shows that the SiGe technology has more efficient leakage-delay and dynamic energy-delay trade-offs at nominal supply. These advantages of SiGe VLSI circuits are further emphasized at low voltages. This demonstrates that SiGe VLSI circuits benefit from aggressive voltage scaling significantly more than Si circuits, thereby making SiGe pMOSFET a mature candidate to substitute Si transistor for VLSI system implementations in future technology nodes. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISCAS.2011.5938049 | Circuits and Systems |
Keywords | Field | DocType |
Ge-Si alloys,MOSFET,VLSI,high-k dielectric thin films,logic circuits,SiGe,VLSI logic circuits,aggressive dynamic voltage scaling,buried pMOSFET,circuit-level metrics,dynamic energy-delay trade-offs,high-k-metal gate stack,leakage-delay trade-offs,size 45 nm,system-level metrics,wafer-level measurements | Dynamic voltage scaling,Logic gate,Computer science,Electronic engineering,MOSFET,Electronic circuit,Transistor,Metal gate,Very-large-scale integration,Electrical engineering,Silicon-germanium | Conference |
ISSN | ISBN | Citations |
0271-4302 E-ISBN : 978-1-4244-9472-9 | 978-1-4244-9472-9 | 1 |
PageRank | References | Authors |
0.45 | 6 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| F. Crupi | 1 | 130 | 24.33 |
| M. Alioto | 2 | 188 | 23.70 |
| Jacopo Franco | 3 | 22 | 18.53 |
| P. Magnone | 4 | 19 | 5.90 |