Name
Abstract | ||
|---|---|---|
This paper described a model-order reduction (MOR) method based on a novel pure-nodal analysis formulation (PNA) which permits the use of symmetric, positive-definite Cholesky solvers for all circuit topologies. Moreover, frequently occurring special cases, e.g., inductor-resistor tree structures result in particular types of matrices that are solved by an even faster linear time algorithm. The model order reduction algorithms also uses symmetric-Lanczos iteration and non- standard inner-products for generating the Krylov subspace basis. Its efficiency is supported by a wide range of industrial examples. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISCAS.2011.5938110 | Circuits and Systems |
Keywords | Field | DocType |
integrated circuit interconnections,iterative methods,matrix algebra,Krylov subspace basis,circuit topologies,inductor-resistor tree structures,linear time algorithm,matrices,nonstandard inner-products,on-chip interconnect model order reduction,positive-definite Cholesky solvers,pure-nodal analysis formulation,symmetric-Lanczos iteration | Krylov subspace,Nodal analysis,Model order reduction,Computer science,Matrix (mathematics),Iterative method,Electronic engineering,Tree structure,Time complexity,Cholesky decomposition | Conference |
ISSN | ISBN | Citations |
0271-4302 E-ISBN : 978-1-4244-9472-9 | 978-1-4244-9472-9 | 0 |
PageRank | References | Authors |
0.34 | 7 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Frank Liu | 1 | 262 | 23.05 |
| Peter Feldmann | 2 | 6 | 1.91 |