Paper Info
Title
A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS
Abstract
A delay-line-based analog-to-digital converter for high-speed applications is introduced. The ADC converts the sampled input voltage to a delay that controls the propagation velocity of a digital pulse. The output digital code is generated based on the propagation length of the pulse in a fixed time window. The effects of quantization noise, jitter, and mismatch are discussed. We show that because of the averaging mechanism of the delay-line, this structure is more power efficient in the presence of noise and mismatch in deep sub-micron CMOS. To show the feasibility of this approach, a 4 bit 1.2 GS/s ADC is designed and fabricated in 65 nm CMOS in an active area of 110 μm × 105 μm. The measured INL and DNL of the ADC are below 0.8 bits and 0.5 bits and it achieves an SNDR of 20.4 dB at Nyquist rate. This delay-line-based ADC consumes 2 mW of power from a 1.2 V supply resulting in 196 fJ/conversion step without using any calibration or post-processing.
Year
DOI
Venue
2011
10.1109/JSSC.2011.2162186
Solid-State Circuits, IEEE Journal of
Keywords
Field
DocType
CMOS digital integrated circuits,analogue-digital conversion,DNL,INL,bit rate 1.2 Gbit/s,calibration,delay-line-based ADC,delay-line-based analog-to-digital converter,digital pulse,fixed time window,output digital code,post-processing,power 2 mW,quantization noise,size 65 nm,submicron CMOS process,voltage 1.2 V,word length 0.5 bit,word length 0.8 bit,word length 4 bit,Analog-to-digital converter,CMOS,delay-cell,delay-line,low-power,scaling,time-to-digital conversion
4-bit,Dynamic range,Computer science,CMOS,Analog-to-digital converter,Effective number of bits,Electronic engineering,Jitter,Quantization (signal processing),Nyquist rate
Journal
Volume
Issue
ISSN
46
10
0018-9200
Citations 
PageRank 
References 
21
1.38
24
Authors
2
Name
Order
Citations
PageRank
Yahya M. Tousi116113.68
Ehsan Afshari232536.65