Name
Title | ||
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Reduction of minimum operating voltage (VDDmin) of CMOS logic circuits with post-fabrication automatically selective charge injection |
Abstract | ||
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In order to reduce minimum operating voltage (VDDmin) of CMOS logic circuits, a new method reducing the within-die random threshold (VTH) variation of transistors by a post-fabrication automatically selective charge injection using substrate hot electrons (SHE) is proposed along with novel circuitry to utilize this. In the new circuit, switches are added to combinational logic circuits in order to turn them into latch loops. In order to reduce VDDmin, design guides on the optimal (1) loop topology, (2) number of stages in a loop, (3) VTH shift per charge injection, and (4) number of charge injection trials are explored through simulations. By applying the proposed scheme to 96-stage inverter chain fabricated in 65-nm CMOS, the measured reduction of VDDmin from 94mV to 74mV is successfully demonstrated for the first time.
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Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISLPED.2011.5993632 | international symposium on low power electronics and design |
Keywords | DocType | ISSN |
CMOS logic circuits,hot carriers,96-stage inverter chain,CMOS logic circuits,SHE,post-fabrication automatically selective charge injection,size 65 nm,substrate hot electrons,voltage 94 mV to 74 mV | Conference | Pending E-ISBN : 978-1-61284-659-0 |
ISBN | Citations | PageRank |
978-1-61284-659-0 | 0 | 0.34 |
References | Authors | |
8 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Honda, K. | 1 | 0 | 0.34 |
| Ikeuchi, K. | 2 | 203 | 20.27 |
| Nomura, M. | 3 | 14 | 4.97 |
| Makoto Takamiya | 4 | 395 | 79.98 |