Title
High-level synthesis for multi-cycle transient fault tolerant datapaths
Abstract
As the advance in semiconductor technology, the tolerance for transient faults caused by particle strike, called SET (single event transient), becomes an important issue, and moreover future technologies bring the possibility of occurrence of long duration errors spanning across multiple cycles of the circuits due to particle strike. In this paper we discuss high-level synthesis for multi-cycle transient fault tolerant datapaths. Clarifying the conditions for multi-cycle error correctability and detectability of multi-cycle transient fault tolerant datapaths, we propose a heuristic algorithm for finding optimal operator binding of kc-cycle error correctable / kd-cycle error detectable datapaths with minimum operators. The method focuses on only transient faults (not permanent ones), and therefore it can derive appropriate designs necessary and sufficient for tolerance of SET avoiding use of excessive hardware resources.
Year
DOI
Venue
2011
10.1109/IOLTS.2011.5993804
IOLTS
Keywords
Field
DocType
set,fault tolerant system,soft error,heuristic algorithm,error detection and correction,fault tolerance,error correction,error detection,fault tolerant,high level synthesis
Semiconductor technology,Heuristic (computer science),Computer science,High-level synthesis,Parallel computing,Real-time computing,Electronic engineering,Fault tolerance,Operator (computer programming),Transient analysis,Electronic circuit
Conference
ISSN
ISBN
Citations 
1942-9398
978-1-4577-1053-7
4
PageRank 
References 
Authors
0.54
6
4
Name
Order
Citations
PageRank
Tomoo Inoue135247.23
H. Henmi240.54
Hiroshi Yoshikawa3263.51
H. Ichihara440.54