Paper Info
Title
ASIC implementation of a hardware-embedded physical unclonable function
Abstract
Within-die variations in path delays are increasing with scaling. Although higher levels of within-die delay variations are undesirable from a design perspective, they represent a rich source of entropy for applications that make use of `secrets', such as authentication, hardware metering and encryption. Physical unclonable functions or PUFs are a class of circuit primitives that leverage within-die variations as a means of generating random bitstrings for these types of applications. In this study, the authors present test chip results of a hardware-embedded delay PUF (HELP) that extracts entropy from the stability characteristics and within-die variations in path delays. HELP obtains accurate measurements of path delays within core logic macros using an embedded test structure called regional delay behaviour (REBEL). REBEL provides capabilities similar to an off-chip logic analyser, and allows very fast analysis of the temporal behaviour of signals emerging from paths in a core logic macro. Statistical characteristics related to the randomness, reproducibility and uniqueness of the bitstrings produced by HELP are evaluated across industrial-level temperature and supply voltage variations.
Year
DOI
Venue
2014
10.1049/iet-cdt.2014.0042
Computers & Digital Techniques, IET
Keywords
DocType
Volume
application specific integrated circuits,cryptography,entropy,logic analysers,ASIC,HELP,REBEL,core logic macros,embedded test structure,encryption,entropy,hardware metering,hardware-embedded delay PUF,hardware-embedded physical unclonable function,industrial-level temperature,off-chip logic analyser,path delays,supply voltage variations,temporal behaviour,within-die delay variations
Journal
8
Issue
ISSN
Citations 
6
1751-8601
3
PageRank 
References 
Authors
0.37
11
4
Name
Order
Citations
PageRank
Fareena Saqib1308.89
Matthew Areno2152.47
Jim Aarestad3192.25
James F. Plusquellic410915.02