Name
Abstract | ||
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This paper studies alternative Network-on-Chip architectures for emerging many-core chip multiprocessors, by exploring the following design options on mesh-based networks: Multiple physical networks (P), cores concentration (C), express channels (X), flit widths (W), and virtual channels (V). We exhaustively evaluate all combinations of the aforementioned parameters (P, C, X, W, V), using the energy-throughput ratio (ETR) as a metric to classify network configurations. Our experimental results show that, on one hand, with an appropriate selection of parameters (V,W), an optimized baseline 2D mesh offers the best possible ETR for NoCs with up to a few tens of cores (64-core NoC). More complicated networks, using concentration and express channels, can reduce the zero-load latency, but do not necessarily help to improve ETR. On the other hand, for larger CMPs, a 2D mesh with multiple physical networks is a better option: once optimized, this architectural choice can reduce the ETR by up to 46% for 256 cores.
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Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ANCS.2015.7110129 | Architectures for Networking and Communications Systems |
Keywords | Field | DocType |
Network-on-chip,mesh,energy,multiple networks,express channels,concentration,virtual channels,flit widths,latency,energy to throughput | Computer science,Latency (engineering),Parallel computing,Communication channel,Computer network,Network on a chip,Chip,Real-time computing,Throughput | Conference |
ISBN | Citations | PageRank |
978-1-4673-6632-8 | 3 | 0.38 |
References | Authors | |
32 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Antonis Psathakis | 1 | 5 | 1.13 |
| Vassilis Papaefstathiou | 2 | 97 | 13.71 |
| Nikolaos Chrysos | 3 | 60 | 8.56 |
| Fabien Chaix | 4 | 11 | 0.93 |
| Evangelos Vasilakis | 5 | 8 | 2.48 |
| Dionisios N. Pnevmatikatos | 6 | 982 | 106.40 |
| Manolis Katevenis | 7 | 378 | 36.21 |