Name
Title | ||
|---|---|---|
Efficient FPGA implementation of an adaptive IQ-imbalance corrector for communication receivers using reduced range multipliers |
Abstract | ||
|---|---|---|
Digital signal processing techniques for compensating the IQ-imbalances in quadrature receivers are paving the path towards software-configurable-radio-receivers. Unsupervised signal processing algorithms operating at the baseband have been developed to deal with these impairments. This paper deals with an efficient FPGA implementation of an adaptive IQ-imbalance corrector using reduced range multipliers. Use of reduced-range multipliers result in 40% reduction in area and power consumption without a compromise in performance when compared with an efficiently designed general purpose multiplier approach. |
Year | Venue | Keywords |
|---|---|---|
2005 | Antalya | digital signal processing chips,field programmable gate arrays,radio receivers,software radio,fpga implementation,adaptive iq-imbalance corrector,communication receivers,digital signal processing,reduced range multipliers,software-configurable-radio-receivers,unsupervised signal processing algorithms,bit error rate,dynamic range,adaptive systems,hardware |
Field | DocType | ISBN |
Baseband,Digital signal processing,Adaptive beamformer,Dynamic range,Adaptive system,Computer science,Field-programmable gate array,Electronic engineering,Multiplier (economics),Real-time computing,Bit error rate | Conference | 978-160-4238-21-1 |
Citations | PageRank | References |
2 | 0.43 | 2 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ediz Çetin | 1 | 53 | 13.67 |
| Süleyman Sirri Demirsoy | 2 | 57 | 8.72 |
| Izzet Kale | 3 | 330 | 62.09 |
| Richard C. S. Morling | 4 | 62 | 18.35 |