Name
Abstract | ||
|---|---|---|
The low-density parity-check (LDPC) coded bitinterleaved coded modulation with iterative demapping (BICMID) has excellent bit error rate (BER) performance, but with extremely high receiver complexity. This paper proposes a threestage full-parallel receiver architecture, in which each component decoder is separately but simultaneously iteratively decoded. This architecture can make full use of the computing resources and improve the system performance without sacrificing the throughput. Three-dimensional (3-D) extrinsic information transfer (EXIT) analysis and BER simulations are carried out to demonstrate the superiority of the proposed new receiver architecture. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/LCOMM.2015.2426694 | Communications Letters, IEEE |
Keywords | Field | DocType |
Receivers,Iterative decoding,Computer architecture,Decoding,Bit error rate,Modulation | Architecture,Information transfer,Low-density parity-check code,Computer science,Modulation,Real-time computing,Coded modulation,Throughput,Decoding methods,Bit error rate | Journal |
Volume | Issue | ISSN |
PP | 99 | 1089-7798 |
Citations | PageRank | References |
2 | 0.40 | 7 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cheng-Te Lin | 1 | 2 | 0.74 |
| Kewu Peng | 2 | 279 | 39.52 |
| Zaishuang Liu | 3 | 56 | 4.81 |
| Zhixing Yang | 4 | 1003 | 87.79 |