Name
Title | ||
|---|---|---|
Hybrid floating-point modules with low area overhead on a fine-grained processing core |
Abstract | ||
|---|---|---|
This paper proposes Hybrid Floating-Point Modules (HFPMs) as a method to improve software floating-point (FP) throughput without incurring the area overhead of hardware floating-point units (FPUs). The proposed HFPMs were synthesized in 65 nm CMOS. They increase throughput over a fixed-point software FP implementation by 3.6× for addition/subtraction, 2.3× for multiplication, and require less area than hardware modules. Nine functionally equivalent FPU implementations using combinations of software, hardware, and hybrid modules are synthesized and provide 1.07-3.34× higher throughput than a software FPU implementation, while requiring 1.08-12.5× less area than a hardware FPU for multiply-add operations. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ACSSC.2014.7094784 | Pacific Grove, CA |
Keywords | Field | DocType |
CMOS digital integrated circuits,floating point arithmetic,CMOS,FPU,HFPM synthesis,addition operation,fine-grained processing core,fixed-point software FP implementation,hardware FPU,hardware floating-point units,hardware module,hybrid floating-point modules,hybrid module,low-area overhead,multiplication operation,multiply-add operations,size 65 nm,software FP throughput improvement,software floating-point throughput improvement,software module,subtraction operation | Computer science,Floating point,Implementation,CMOS,Multiplication,Software,Throughput,Subtraction,Hardware modules,Embedded system | Conference |
ISSN | ISBN | Citations |
1058-6393 | 978-1-4799-8295-0 | 3 |
PageRank | References | Authors |
0.44 | 7 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jon J. Pimentel | 1 | 58 | 4.50 |
| Baas, B.M. | 2 | 67 | 3.81 |