Name
Abstract | ||
|---|---|---|
In this paper, a novel erase method is proposed to modulate the electron tunneling region of 40 nm NAND flash memory device. The erasing electron can move to gate center from gate edge under back bias at 0.3V/-0.8V. The Fowler-Nordheim (FN) current of erase stress distributes on the whole channel region, not located at the gate edge region. Results show that the proposed method can improve cell reliability about 33%. TCAD analysis is employed to explain and prove the mechanism. This novel erase method is promising for scaled NAND flash memory. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/VLSI-TSA.2015.7117583 | Microelectronics Reliability |
DocType | Volume | Citations |
Journal | 72 | 0 |
PageRank | References | Authors |
0.34 | 1 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| chanching lin | 1 | 0 | 0.34 |
| kueishu changliao | 2 | 0 | 0.34 |
| chenhao huang | 3 | 0 | 0.34 |
| yichung liang | 4 | 0 | 0.34 |
| Tzung-Bin Huang | 5 | 0 | 0.68 |
| Hann-Ping Hwang | 6 | 0 | 1.01 |