Name
Abstract | ||
|---|---|---|
In this paper, a design flow for the design of calibrated pipeline analog-to-digital converters (ADCs), and a framework for their behavioral modeling is presented. The model includes also second order effects such as nonlinearities and linear and non-linear memory errors, thus allowing fast and accurate simulations of the ADC behavior. In this way, background calibration techniques can be simulated during the design phase, allowing the optimization of ADC performance even under process variations. The design flow can be used to extract information about sensitivity to operating and environmental conditions, post-calibration performance and also design yield, by extracting a database of Monte Carlo realizations of the ADC stages, so that it can be employed to optimize system and circuit design. Simulations using a O.13-µm CMOS technology show an accuracy of the model as high as 17 bits. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TCSI.2009.2033532 | Circuits and Systems I: Regular Papers, IEEE Transactions |
Keywords | Field | DocType |
CMOS integrated circuits,analogue-digital conversion,calibration,integrated circuit design,CMOS technology,Monte Carlo realizations,analog-to-digital converters,background calibration techniques,behavioral modeling,information extraction,linear memory errors,nonlinear memory errors,second order effects,size 0.13 mum,Pipeline analog-to-digital converters (ADCs),behavioral models,design yield,digital background calibration | Monte Carlo method,Computer science,Behavioral modeling,Circuit design,Converters,Design flow,Electronic engineering,CMOS,Integrated circuit design,Calibration | Journal |
Volume | Issue | ISSN |
57 | 6 | 1549-8328 |
Citations | PageRank | References |
9 | 0.66 | 21 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Centurelli, F. | 1 | 13 | 2.17 |
| Monsurrò, P. | 2 | 9 | 0.66 |
| Trifiletti, A. | 3 | 15 | 2.64 |