Paper Info
Title
Performance analysis of compressed instruction sets on workloads targeted at mobile internet devices
Abstract
This paper describes the performance advantages of a two and four byte variable length instruction set, Thumb2, over a four byte fixed length instruction set, ARM. Both instruction sets are found in ARMv7-A ISA compatible processors, such as the ARM Cortex-A8 and Cortex-A9. The code size reduction when using a variable length instruction set is well understood and can be significant. The focus of this paper is the performance advantage of increased code density. With Thumb2 more instructions are stored in the I-cache, increasing I-cache hit rates, and in turn increasing the performance of the processor. To demonstrate the performance advantage of Thumb2, a Mozilla based Web browser built for Thumb2 and ARM on Linux is run in a full system emulator and in a full system instruction set simulator with a cache model. Switching from the ARM four byte fixed length instruction set to the Thumb2 two and four byte variable length instruction set results in a 1.07× improvement in performance and 33% improvement in code density.
Year
DOI
Venue
2009
10.1109/SOCCON.2009.5398056
Belfast
Keywords
Field
DocType
Internet,Linux,cache storage,instruction sets,online front-ends,performance evaluation,ARM,ARM Cortex-A8,ARMv7-A ISA,Cortex-A9,I-cache,Linux,Mozilla,Thumb2,Web browser,code density,code size reduction,compressed instruction sets,fixed length instruction set,mobile Internet devices,performance analysis
Application-specific instruction-set processor,Instruction register,Instruction set,Computer science,Real-time computing,Addressing mode,Orthogonal instruction set,Computer hardware,Minimal instruction set computer,Self-modifying code,Operating system,Instruction path length
Conference
ISSN
ISBN
Citations 
2164-1676
978-1-4244-4941-5
2
PageRank 
References 
Authors
0.58
2
4
Name
Order
Citations
PageRank
Chander Sudanthi120.58
Mrinmoy Ghosh220.58
Kevin Welton320.58
Nigel C. Paver420.58