Paper Info
Title
A multi-banked shared-l1 cache architecture for tightly coupled processor clusters
Abstract
A shared-L1 cache architecture is proposed for tightly coupled processor clusters. Sharing an L1 tightly coupled data memory (TCDM) among a significant (up to 16) number of processors is challenging in terms of speed. Sharing L1 cache is even more challenging, since operation is more complex, as it eases programming. The feasibility in terms of performance of shared TCDM was shown in ST Microelectronics platform 2012, but the performance cost of supporting shared L1 cache remains to be proven. In this paper we show that replacing TCDM with a multi-banked shared-L1 cache imposes limited speed overhead. Of course, it comes at the cost of area and power. We explore the shared L1 cache architecture in terms of number of processing elements (PEs) and cache banks. Experimental results show that our multi-banked shared-L1 cache can operate with almost the same frequency as that of related TCDM architecture if the cache controller uses a cache line of 4 words. Results also show that, the area overhead with respect to TCDM is less than 18% for a cluster containing 16 Leon3 processors and 32 cache banks. We also show that the overhead on MIPS/Watt and MIPS/mm2 is from 5% to 30% depending on the size of processor in the cluster for a 16×32 configuration (16 cores and 32 cache/memory banks).
Year
DOI
Venue
2012
10.1109/ISSoC.2012.6376362
System Chip
Keywords
Field
DocType
cache storage,microprocessor chips,ST Microelectronics platform 2012,TCDM,multibanked shared-l1 cache architecture,tightly coupled data memory,tightly coupled processor cluster
Pipeline burst cache,Cache invalidation,Cache pollution,Computer science,Cache,Parallel computing,Page cache,Cache algorithms,Cache coloring,Smart Cache,Embedded system
Conference
ISBN
Citations 
PageRank 
978-1-4673-2894-4
1
0.37
References 
Authors
5
3
Name
Order
Citations
PageRank
Mohammad Reza Kakoee1723.99
Vladimir Petrovic220.72
Luca Benini3131161188.49