Paper Info
Title
The Dawn of 22nm Era: Design and CAD Challenges
Abstract
Technology scaling clearly has been the driver of semiconductor and thereby EDA industry. In the semiconductor industry today, 45 nm CMOS designs are in full production and 32 nm design rules and infrastructure are already in place for designs starting later this year. It will not be long before the beat of 22 nm will be upon us. Due to ever increasing cost of doing design, design productivity and more specifically, cost of design has become a major bottleneck in large scale design projects. Due to this cost crunch, automated synthesis techniques have been becoming increasingly important and this is bound to become a major trend going into 22 nm for high performance SoCs. In addition, in 22 nm and beyond, 3D IC technology has the potential of easing the system performance challenge problem. In order to exploit the full potential of 3D technology, new challenges in the area of physical design, thermal analysis, system level design and analysis need to be addressed. 3D interconnects have the potential of reducing critical paths delays significantly, which are typically between memory and the interfacing logic. In addition, now that the physical limits are beginning to impact scaling, the question is: how can we cost effectively design with complicated technology requirements presented by 22 nm node and how the design automation community can help to achieve this goal? What are the challenges at 22 nm and what would design look like going into 22 nm and beyond? In this paper, we will focus on the major design and CAD challenges associated with 22 nm and beyond.
Year
DOI
Venue
2010
10.1109/VLSI.Design.2010.85
VLSI Design
Keywords
Field
DocType
CMOS integrated circuits,circuit CAD,design engineering,integrated circuit design,nanoelectronics,semiconductor industry,system-on-chip,three-dimensional integrated circuits,3D IC technology,3D interconnects,CAD challenges,CMOS design,EDA industry,SoC,automated synthesis techniques,complementary metal-oxide-semiconductor,computer-aided design,critical path delays,design costs,design productivity,electronic design automation,integrated circuits,interfacing logic,large scale design projects,physical design challenges,semiconductor industry,size 22 nm,system level analysis,system level design,system performance challenges,system-on-chip,technology scaling,thermal analysis,22nm CMOS,3D ICs,Automated Synthesis,Design Productivity,VLSI CAD Challenges,VLSI Design Challenges,VLSI Physical design
Bottleneck,Computer science,Electronic system-level design and verification,Design technology,Electronic engineering,Exploit,Integrated circuit design,Electronic design automation,Three-dimensional integrated circuit,Physical design
Conference
ISSN
ISBN
Citations 
1063-9667
978-1-4244-5541-6
7
PageRank 
References 
Authors
1.03
7
2
Name
Order
Citations
PageRank
Ruchir Puri171.03
David S. Kung216620.93