Name
Title | ||
|---|---|---|
Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks |
Abstract | ||
|---|---|---|
Cryptographic circuits are subject to sneak attacks that target directly their implementation. So-called side-channel analyses consist in observing dynamic circuit emanations in order to derive information about the secrets it conceals. Clock-less logic styles natively make side-channel attacks difficult, because of the absence of timing references for the algorithm beginning or ending. We present two ways to implement secure clock-less cryptographic circuits. The first one is based on a local synchronization at the gate level, and helps achieving close to constant emanations. The second one is more audacious as it is based merely on removing all synchronization. This approach proves to be very promising in terms of protection against side-channel attacks, while keeping a reasonable overhead both in terms of cost and performance. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ICECS.2009.5411008 | Yasmine Hammamet |
Keywords | Field | DocType |
cryptography,logic gates,synchronisation,clock-less logic,cryptographic circuit,dynamic circuit emanation,gate level,local synchronization,side-channel attack,sneak attack | Synchronization,Logic gate,Pass transistor logic,Cryptography,Computer security,Computer science,Encryption,Side channel attack,Logic family,Electronic circuit | Conference |
ISBN | Citations | PageRank |
978-1-4244-5091-6 | 2 | 0.38 |
References | Authors | |
5 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Guilley, S. | 1 | 2 | 0.38 |
| Chaudhuri, S. | 2 | 10 | 1.14 |
| Sauvage, L. | 3 | 2 | 0.38 |
| J-L. Danger | 4 | 125 | 9.83 |