Name
Abstract | ||
|---|---|---|
Trace-driven simulation is a widely used technique to study computer architecture systems and to evaluate micro architecture features. A trace may contain execution information for billions or even trillions of instructions and storing these traces is a challenge itself. In this paper we describe VITC, a one-pass trace compression tool based in streams. VITC is based on SBC and compresses traces by exploiting the natural instruction and data redundancy in instruction streams. The VITC is capable of compressing traces of variable-length instructions, such as x86 instruction traces, and produces compressed files 87 times smaller than gzip and 47 times smaller than bzip2. The compressed traces produced by VITC are, on average, 1200 times smaller than the original ones. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/WSCAD-SSC.2012.38 | WSCAD-SSC '12 Proceedings of the 2012 13th Symposium on Computing Systems |
Keywords | Field | DocType |
computer architecture,data compression,digital simulation,SBC,VITC,computer architecture systems,data redundancy,instruction streams,microarchitecture features,natural instruction,one-pass trace compression tool,trace-driven simulation,variable-length instruction trace compression,x86 instruction traces | x86,Trace compression,Computer science,Instruction set,Parallel computing,Data redundancy,Data compression,Computer hardware,Microarchitecture | Conference |
ISBN | Citations | PageRank |
978-1-4673-4468-5 | 0 | 0.34 |
References | Authors | |
6 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Raphael Moreira Zinsly | 1 | 0 | 0.34 |
| Sandro Rigo | 2 | 185 | 24.91 |
| Edson Borin | 3 | 1 | 2.71 |