Name
Abstract | ||
|---|---|---|
In this brief, a new low-power level shifter (LS) is presented for robust logic voltage shifting from near/sub-threshold to above-threshold domain. The new circuit combines the multi-threshold CMOS technique along with novel topological modifications to guarantee a wide voltage conversion range with limited static power and total energy consumption. When implemented in a 90-nm technology process, the proposed design reliably converts 180-mV input signals into 1-V output signals, while maintaining operational frequencies above 1-MHz, also taking into account process-voltage-temperature variations.Post-layout simulation results demonstrate that the new LS reaches a propagation delay less than 22 ns, a static power dissipation of only 6.4 nW, and a total energy per transition of only 74 fJ for a 0.2-V 1-MHz input pulse. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TCSII.2012.2231037 | Circuits and Systems II: Express Briefs, IEEE Transactions |
Keywords | Field | DocType |
CMOS integrated circuits,circuit layout,circuit simulation,low-power electronics,network synthesis,power supply circuits,above-threshold domain,frequency 1 MHz,level shifter,logic voltage shifting,multisupply voltage design,multithreshold CMOS technique,post-layout simulation,power 6.4 nW,size 90 nm,topological modification,voltage 0.2 V,voltage 1 V,voltage 180 mV,Level shifter (LS),multi-supply voltage design,sub-threshold operation,ultra-low power | CPU core voltage,Voltage optimisation,Electronic engineering,Voltage regulation,Logic level,Electrical engineering,Mathematics,Switched-mode power supply,Voltage regulator,Voltage divider,Dropout voltage | Journal |
Volume | Issue | ISSN |
59 | 12 | 1549-7747 |
Citations | PageRank | References |
26 | 1.61 | 11 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lanuzza, M. | 1 | 26 | 1.94 |
| Pasquale Corsonello | 2 | 37 | 2.46 |
| Stefania Perri | 3 | 41 | 2.91 |