Paper Info
Title
A tightly-coupled multi-core cluster with shared-memory HW accelerators
Abstract
Tightly coupling hardware accelerators with processors is a well-known approach for boosting the efficiency of MPSoC platforms. The key design challenges in this area are: (i) streamlining accelerator definition and instantiation and (ii) developing architectural templates and run-time techniques for minimizing the cost of communication and synchronization between processors and accelerators. In this paper we present an architecture featuring tightly-coupled processors and hardware processing units (HWPU), with zero-copy communication. We also provide a simple programming API, which simplifies the process of offloading jobs to HWPUs.
Year
DOI
Venue
2012
10.1109/SAMOS.2012.6404162
Embedded Computer Systems
Keywords
Field
DocType
application program interfaces,multiprocessing systems,shared memory systems,synchronisation,system-on-chip,API,HWPU,MPSoC platforms,accelerator definition streamlining,accelerator instantiation,architectural templates,communication cost minimization,hardware processing units,multiprocessor system-on-chip technology,run-time techniques,shared memory HW accelerators,synchronization cost minimization,tightly coupling hardware accelerators,tightly-coupled multicore cluster,tightly-coupled processors,zero-copy communication
Computer architecture,Architecture,Synchronization,System on a chip,Shared memory,Computer science,Boosting (machine learning),Template,Multi-core processor,MPSoC,Embedded system
Conference
ISBN
Citations 
PageRank 
978-1-4673-2296-6
9
0.52
References 
Authors
6
4
Name
Order
Citations
PageRank
Dehyadegari, M.190.52
Marongiu, A.2282.08
Mohammad Reza Kakoee3723.99
Luca Benini4131161188.49