Name
Abstract | ||
|---|---|---|
As the complexity of SoC design grows more than 2X a year, the time spent in logic simulation is exponentially growing. It is getting hard to meet the project schedule with existing simulation techniques. This paper proposes a new technique called Incremental Elaboration. The increased design complexity significantly impacts on elaboration time among the simulation process because hundreds of millions modules are elaborated and connected in the elaboration step. The elaboration time often takes more than 5 hours in full timing simulation. Long elaboration time degrades efficiency of verification because verification activity requires a lot of iterations. The elaboration time can be reduced by 80~90% using the proposed Incremental Elaboration technique. Application to the regression environment showed total regression time can be reduced by 42% and disk spaces for regression runs can be reduced by 96%. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISOCC.2012.6407124 | ISOCC |
Keywords | Field | DocType |
formal verification,integrated circuit design,integrated circuit testing,system-on-chip,soc design,elaboration time,incremental elaboration,logic simulation,massive advanced node,project schedule,regression time,regression,testbench,verification,system on chip | Schedule (project management),System on a chip,Intelligent verification,Computer science,Electronic engineering,Real-time computing,Integrated circuit design,Logic simulation,Elaboration,Embedded system,Formal verification | Conference |
ISSN | ISBN | Citations |
2163-9612 | 978-1-4673-2988-0 | 0 |
PageRank | References | Authors |
0.34 | 0 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| d cha | 1 | 0 | 0.34 |
| hyunwoo koh | 2 | 0 | 0.34 |
| namphil jo | 3 | 0 | 0.34 |
| jay b kim | 4 | 0 | 0.34 |
| Byeong Min | 5 | 33 | 5.60 |
| karthik kothandapani | 6 | 0 | 0.34 |
| riccardo oddone | 7 | 1 | 0.72 |
| adam sherer | 8 | 1 | 0.72 |