Name
Title | ||
|---|---|---|
An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording |
Abstract | ||
|---|---|---|
Low power consumption per channel and data rate minimization are two key challenges which need to be addressed in future generations of neural recording systems (NRS). Power consumption can be reduced by avoiding unnecessary processing whereas data rate is greatly decreased by sending spike time-stamps along with spike features as opposed to raw digitized data. Dynamic range in NRS can vary with time due to change in electrode-neuron distance or background noise, which demands adaptability. An analog-to-digital converter (ADC) is one of the most important blocks in a NRS. This paper presents an 8-bit SAR ADC in 0.13-$\\mu{\\rm m}$ CMOS technology along with input and reference buffer. A novel energy efficient digital-to-analog converter switching scheme is proposed, which consumes 37% less energy than the present state-of-the-art. The use of a ping-pong input sampling scheme is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the data rate, the A/D process is only enabled through the in-built background noise rejection logic to ensure that the noise is not processed. The ADC resolution can be adjusted from 8 to 1 bit in 1-bit step based on the input dynamic range. The ADC consumes 8.8 $\\mu{\\rm W}$ from 1 V supply at 1 MS/s speed. It achieves effective number of bits of 7.7 bits and FoM of 42.3 fJ/conversion-step. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TVLSI.2013.2238957 | VLSI) Systems, IEEE Transactions |
Keywords | Field | DocType |
CMOS integrated circuits,analogue-digital conversion,biomedical electronics,biomedical measurement,buffer circuits,data compression,low-power electronics,recording,A/D process,CMOS technology,NRS,SAR ADC,VGA,background noise rejection logic,data rate minimization,electrode-neuron distance,energy efficient digital-to-analog converter switching scheme,input buffer,integrated data compression,low power consumption per channel,neural recording systems,ping-pong input sampling scheme,power 8.8 muW,reference buffer,size 0.13 mum,voltage 1 V,word length 8 bit to 1 bit,Asynchronous,biomedical,digital-to-analog converter (DAC) switching,multichannel,neural,ping-pong,preamplifier,successive approximation register (SAR),threshold,variable gain amplifier,variable resolution | Dynamic range,Background noise,Computer science,Communication channel,Effective number of bits,Electronic engineering,CMOS,Successive approximation ADC,Video Graphics Array,Low-power electronics | Journal |
Volume | Issue | ISSN |
21 | 11 | 1063-8210 |
Citations | PageRank | References |
5 | 0.65 | 16 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vikram Chaturvedi | 1 | 24 | 3.41 |
| Tejasvi Anand | 2 | 5 | 2.01 |
| Bharadwaj Amrutur | 3 | 454 | 80.42 |