Title
Stretching the limits of FPGA SerDes for enhanced ATE performance
Abstract
This paper describes a multi-gigahertz test module to enhance the performance capabilities of automated test equipment (ATE), such as high-speed signal generation, loopback testing, jitter injection, etc. The test module includes a core logic block consisting of a high-performance FPGA. It is designed to be compatible with existing ATE infrastructure; connecting to the device under test (DUT) via a device interface board (DIB). The core logic block controls the test module's functionality, thereby allowing it to operate independently of the ATE. Exploiting recent advances in FPGA SerDes, the test module is able to generate very high (multi-GHz) data rates at a relatively low cost. In this paper we demonstrate multiplexing logic to generate higher data rates (up to 10Gbps) and a low-jitter buffered loopback path to carry high speed signals from the DUT back to the DUT. The test module can generate 10Gbps signals with ~32ps (p-p) jitter, while the loopback path adds ~20ps (p-p) jitter to the input signal.
Year
DOI
Venue
2010
10.1109/DATE.2010.5457212
Design, Automation & Test in Europe Conference & Exhibition
Keywords
Field
DocType
automatic test equipment,field programmable gate arrays,FPGA,SerDes,automated test equipment,core logic block,device interface board,device under test,enhanced ATE performance,high-speed signal generation,jitter injection,loopback testing,Automated Test Equipment(ATE),Field Programmable Gate Array(FPGA),Serializer/Deserializer(SerDes),built-in self test (BIST),high-speed testing,loopback testing,mult-gigahertz testing,test enhancement,test modules
Loopback,Logic gate,Device under test,Computer science,Automatic test equipment,Field-programmable gate array,Logic block,Jitter,Computer hardware,SerDes,Embedded system
Conference
ISSN
ISBN
Citations 
1530-1591
978-1-4244-7054-9
2
PageRank 
References 
Authors
0.39
5
2
Name
Order
Citations
PageRank
Majid, A.M.120.39
David C. Keezer2459.64