Paper Info
Title
Design of a capacitorless low-dropout voltage regulator with fast load regulation in 130nm CMOS
Abstract
This paper describes a low-dropout (LDO) voltage regulator system for portable device applications, with a capacitorless output. The regulator operates with supply voltages from 1.6V to 2V, providing 0.9V to 1.4V regulated voltages at a 99.2% current efficiency. The fully integrated architecture with a 100pF integrated decoupling capacitor was implemented in IBM 130nm CMOS technology, allowing greater power system integration. Post-layout simulations of our design demonstrate that the proposed LDO architecture provides a fast load regulation with a fast 320ns response time for 100mA load current and regulated voltage variations of less than 25mV.
Year
DOI
Venue
2012
10.1109/ICECS.2012.6463549
Electronics, Circuits and Systems
Keywords
Field
DocType
CMOS integrated circuits,capacitors,integrated circuit layout,voltage regulators,CMOS technology,LDO architecture,capacitorless low-dropout voltage regulator,current 100 mA,fast load regulation,integrated decoupling capacitor,portable device applications,post-layout simulations,size 130 nm,time 320 ns,voltage 0.9 V to 1.4 V,voltage 1.6 V to 2 V
Capacitor,Computer science,Control engineering,CMOS,Electronic engineering,Decoupling capacitor,Voltage regulation,Load regulation,Electrical engineering,Voltage regulator,Low-dropout regulator,Dropout voltage
Conference
ISBN
Citations 
PageRank 
978-1-4673-1259-2
0
0.34
References 
Authors
2
2
Name
Order
Citations
PageRank
Antonio David Souza100.34
Sergio Bampi2184.10