Name
Abstract | ||
|---|---|---|
In this paper we describe a Content Addressable Memory (CAM) architecture based on a new custom cell, called XORAM. The cell is composed by two main blocks: a 6T-SRAM, and a 4T-XOR logic gate. Each XORAM cell compares the input data on the bit line with the data stored in the 6T-SRAM cell. The output matching bit is obtained by performing a NOR operation between all bits of the XORAM cells storing the word. The proposed architecture is based on a fully-CMOS combinational logic, and it does nor require any precharge operation or control and timing logic. A compact full-custom layout has been designed for a memory organized in 18-bit words, to reduce both area and power consumption. Compared with a conventional selective precharge match-line technique, the proposed circuit occupies less area. Simulation results demonstrate that power consumption is reduced by a factor of 8. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ICECS.2012.6463629 | Electronics, Circuits and Systems |
Keywords | Field | DocType |
CMOS logic circuits,SRAM chips,content-addressable storage,logic gates,4T-XOR logic gate,6T-SRAM cell,CAM architecture,XOR-based content addressable memory architecture,XORAM,fully-CMOS combinational logic,timing logic | Logic gate,Computer architecture,Sequential logic,Pass transistor logic,AND-OR-Invert,Computer science,Logic optimization,Programmable logic array,Electronic engineering,Logic family,Programmable logic device | Conference |
ISBN | Citations | PageRank |
978-1-4673-1259-2 | 5 | 1.05 |
References | Authors | |
1 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Luca Frontini | 1 | 5 | 1.05 |
| Seyedruhollah Shojaii | 2 | 5 | 1.05 |
| antonino stabile | 3 | 7 | 4.62 |
| Valentino Liberali | 4 | 5 | 1.05 |