Title
Critical path minimized raster scan hardware architecture for computation of the Generalized Hough Transform
Abstract
The Generalized Hough Transform (GHT) is a well known image processing transform to find arbitrary shapes in images. We propose a new raster scan FPGA and VSLI hardware architecture, performing the GHT of a binary template shape with an input image. The architecture has a minimized critical path by the reuse of partial results and the utilization of a flat adder structure. A synchronous pixel pipeline for input image row buffering enables parallel read and write access of the partial results. By this, the architecture's critical path and hence the maximum clock frequency is independent of the template size, content and number of valid pixels in the template. The architecture was implemented on a Xilinx Virtex 5 FPGA device. The design reaches a pixel clock of more than 580 MHz at an exemplary image size of 512×512 pixels and a template size of 64×64 pixels.
Year
DOI
Venue
2012
10.1109/ICECS.2012.6463634
Electronics, Circuits and Systems
Keywords
Field
DocType
Hough transforms,VLSI,critical path analysis,field programmable gate arrays,image processing,FPGA hardware architecture,GHT,VSLI hardware architecture,Xilinx Virtex 5 FPGA device,critical path minimized raster scan hardware architecture,generalized Hough transform,image processing transform
Computer science,Image processing,Electronic engineering,Virtex,Artificial intelligence,Computer vision,Parallel computing,Hough transform,Raster scan,Pixel,Critical path method,Image resolution,Hardware architecture
Conference
ISBN
Citations 
PageRank 
978-1-4673-1259-2
0
0.34
References 
Authors
2
3
Name
Order
Citations
PageRank
Frank Schumacher111.05
Markus Holzer200.34
Thomas Greiner3347.48