Name
Title | ||
|---|---|---|
Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance |
Abstract | ||
|---|---|---|
As power dissipation in future Networks-on-Chips (NoCs) is projected to be a major bottleneck, researchers are actively engaged in developing alternate power-efficient technology solutions. Photonic interconnects is a disruptive technology solution that is capable of delivering the communication bandwidth at low power dissipation when the number of cores is scaled to large numbers. Similarly, 3D stacking is another interconnect technology solution that can lead to low energy/bit for communication. In this paper, we propose to combine photonic interconnects with 3D stacking to develop a scalable, reconfigurable, power-efficient and high-performance interconnect for future many-core systems, called R-3PO (Reconfigurable 3D-Photonic Networks-on-Chip). We propose to develop a multi-layer photonic interconnect that can dynamically reconfigure without system intervention and allocate channel bandwidth from less utilized links to more utilized communication links. In addition to improving performance, reconfiguration can re-allocate bandwidth around faulty channels, thereby increasing the resiliency of the architecture and gracefully degrading performance. For 64-core reconfigured network, our simulation results indicate that the performance can be further improved by 10%-25% for Splash-2, PARSEC and SPEC CPU2006 benchmarks, where as simulation results for 256-core chip indicate a performance improvement of more than 25% while saving 6%-36% energy when compared to state-of-the-art on-chip electrical and optical networks. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/MICRO.2012.34 | Microarchitecture |
Keywords | Field | DocType |
bandwidth allocation,fault tolerance,integrated optics,network-on-chip,optical interconnections,three-dimensional integrated circuits,3D photonic network-on-chip dynamic reconfiguration,3D stacking,64-core reconfigured network,NoC,PARSEC,R-3PO,SPEC CPU2006 benchmarks,Splash-2,channel bandwidth allocation,communication bandwidth,communication links,fault tolerance,high-performance interconnect,low power dissipation,many-core systems,multilayer photonic interconnect,on-chip electrical networks,optical networks,photonic interconnects,power dissipation,power-efficient interconnect,reconfigurable 3D-photonic network-on-chip,Fault Tolerance,Networks-on-Chip (NoC),Photonic,Reconfiguration | Bottleneck,Computer science,Parallel computing,Communication channel,Chip,Fault tolerance,Bandwidth (signal processing),Control reconfiguration,Embedded system,Scalability,Performance improvement | Conference |
ISSN | ISBN | Citations |
1072-4451 | 978-1-4673-4819-5 | 24 |
PageRank | References | Authors |
0.84 | 24 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Randy Morris | 1 | 24 | 0.84 |
| Avinash Karanth Kodi | 2 | 47 | 3.28 |
| Ahmed Louri | 3 | 398 | 47.97 |