Name
Title | ||
|---|---|---|
Information-theoretic tradeoffs of throughput and chip power consumption for decoding error-correcting codes |
Abstract | ||
|---|---|---|
The purpose of this paper is to develop an information-theoretic understanding of the tradeoffs between decoder power, probability of error and decoding throughput. We start by considering the power consumed in the decoder circuit's interconnects, modeled as a lumped capacitor and resistor. After making simplifying assumptions about the decoder circuit, we use a sphere-packing technique to lower bound the decoding error probability for a given number of clock-cycles (or iterations). The analysis can be used to give lower bounds on probability of error versus total decoding power at a fixed decoding throughput. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ISIT.2010.5513731 | Information Theory Proceedings |
Keywords | Field | DocType |
decoding,error correction codes,error statistics,power consumption,JSIT decoder power,chip power consumption,clock-cycles,decoding throughput,error probability,error-correcting codes,information-theoretic tradeoffs,lumped capacitor,resistor,sphere-packing technique | Discrete mathematics,Sequential decoding,Noise measurement,Computer science,Upper and lower bounds,Algorithm,Real-time computing,Chip,Soft-decision decoder,Decoding methods,Throughput,List decoding | Conference |
ISBN | Citations | PageRank |
978-1-4244-7891-0 | 1 | 0.41 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Grover, P. | 1 | 438 | 38.27 |
| Hari Palaiyanur | 2 | 1 | 0.41 |
| A. Sahai | 3 | 1888 | 198.31 |