Name
Title | ||
|---|---|---|
Redundancy reduction for high-speed fir filter architectures based on carry-save adder trees |
Abstract | ||
|---|---|---|
In this work we consider high-speed FIR filter architectures implemented using, possibly pipelined, carry-save adder trees for accumulating the partial products. In particular we focus on the mapping between partial products and full adders and propose a technique to reduce the number of carry-save adders based on the inherent redundancy of the partial products. The redundancy reduction is performed on the bit-level to also work for short wordlength data such as those obtained from sigma-delta modulators. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ISCAS.2010.5537997 | Circuits and Systems |
Keywords | Field | DocType |
FIR filters,adders,carry-save adder trees,high-speed FIR filter architectures,redundancy reduction | Pipeline transport,Adder,Computer science,Interpolation,Electronic engineering,Redundancy (engineering),Carry-save adder,Computer hardware,Finite impulse response | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4244-5309-2 | 1 |
PageRank | References | Authors |
0.47 | 8 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Anton Blad | 1 | 19 | 3.95 |
| Oscar Gustafsson | 2 | 133 | 14.34 |