Name
Title | ||
|---|---|---|
A high-throughput, adaptive FFT architecture for FPGA-based space-borne data processors |
Abstract | ||
|---|---|---|
Historically, computationally-intensive data processing for space-borne instruments has heavily relied on ground-based computing resources. But with recent advances in functional densities of Field-Programmable Gate-Arrays (FPGAs), there has been an increasing desire to shift more processing on-board; therefore relaxing the downlink data bandwidth requirements. Fast Fourier Transforms (FFTs) are commonly-used building blocks for data processing applications, with a growing need to increase the FFT block size. Many existing FFT architectures have mainly emphasized on low power consumption or resource usage; but as the block size of the FFT grows, the throughput is often compromised first. In addition to power and resource constraints, space-borne digital systems are also limited to a small set of space-qualified memory elements, which typically lag behind the commercially available counterparts in capacity and bandwidth. The bandwidth limitation of the external memory creates a bottleneck for a large, high-throughput FFT design with large block size. In this paper, we present the Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture for a moderately large block size (32K) with considerations to power consumption and resource usage, as well as throughput. We will also show that the architecture can be easily adapted for different FFT block sizes with different throughput and power requirements. The result is completely contained within an FPGA without relying on external memories. Implementation results are summarized. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/AHS.2010.5546270 | Adaptive Hardware and Systems |
Keywords | Field | DocType |
fast fourier transforms,signal processing,high throughput,microelectronics,computer architecture,field programmable gate arrays,throughput,bandwidth,kernel functions,external memory,fast fourier transform,computer storage devices,data storage,data processing,kernel,space missions,fourier transformation,low power electronics,field programmable gate array | Block size,Bottleneck,Computer science,Computer data storage,Real-time computing,Bandwidth (signal processing),Fast Fourier transform,Throughput,Energy consumption,Auxiliary memory | Conference |
ISBN | Citations | PageRank |
978-1-4244-5888-2 | 1 | 0.37 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kayla Nguyen | 1 | 1 | 0.37 |
| Jason Zheng | 2 | 1 | 0.37 |
| Yutao He | 3 | 1 | 0.37 |
| Biren Shah | 4 | 1 | 0.37 |