Name
Abstract | ||
|---|---|---|
This paper presents a 3-GS/s 5-bit interpolated Flash ADC with a wideband input buffer amplifier. Small input capacitance of the ADC is necessary to achieve high signal bandwidth with low power consumption of the input buffer. The design challenge is a reduction of power consumption of the interpolated Flash ADC and the input buffer simultaneously. To solve this, the interpolation technique using reference voltages is proposed to reduce the input capacitance and interpolated stages simultaneously. The prototype is fabricated in a 65-nm CMOS technology. The measured results show that the cutoff frequency is 1.6 GHz, the peak spurious-free dynamic range (SFDR) and signal to noise and distortion ratio (SNDR) are 33.1 dB and 23.1 dB at nyquist frequency, respectively. The power consumption including the input buffer is 39.4 mW, and the Figure of Merit (FoM) of 0.58 pJ/conversion-step is achieved. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/VLDI-DAT.2013.6533840 | VLSI Design, Automation, and Test |
Keywords | Field | DocType |
cmos analogue integrated circuits,amplifiers,analogue-digital conversion,buffer circuits,power consumption,cmos technology,sfdr,sndr,flash adc interpolation,frequency 1.6 ghz,gain 33.1 db to 23.1 db,input capacitance,peak spurious-free dynamic range,power 39.4 mw,reference voltages,size 65 nm,small input capacitance,wideband input buffer amplifier,word length 5 bit,capacitance,interpolation | Wideband,Nyquist frequency,Computer science,Signal-to-noise ratio,Buffer amplifier,Flash ADC,Spurious-free dynamic range,Figure of merit,Electronic engineering,Bandwidth (signal processing),Electrical engineering | Conference |
ISSN | ISBN | Citations |
2474-2724 | 978-1-4673-4435-7 | 2 |
PageRank | References | Authors |
0.44 | 3 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| junya matsuno | 1 | 30 | 3.05 |
| masahiro hosoya | 2 | 3 | 1.17 |
| Masanori Furuta | 3 | 17 | 4.42 |
| Tetsuro Itakura | 4 | 187 | 33.44 |