Name
Abstract | ||
|---|---|---|
A method of optimal memory fault repair that differs from analogs by application of algebra-logical technology of fault covering by two-dimensional memory matrix topology is proposed. It results in obtaining minimal and full solutions for subsequent repair in real time, which is based on utilization of spares in memory rows and columns. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/EWDTS.2008.5580144 | Design & Test Symposium |
Keywords | Field | DocType |
algebra,digital storage,fault diagnosis,network topology,system-on-chip,SoC faulty memory cells,algebra-logical technology,embedded repair,fault covering,fault diagnosis,memory columns,memory fault repair,memory rows,two-dimensional memory matrix topology | Boolean function,Row and column spaces,System on a chip,Matrix (mathematics),Computer science,Parallel computing,Network topology,Theoretical computer science,Construction industry,Minification,Maintenance engineering | Conference |
ISBN | Citations | PageRank |
978-1-4244-3403-9 | 0 | 0.34 |
References | Authors | |
8 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vladimir Hahanov | 1 | 0 | 0.34 |
| Eugenia Litvinova | 2 | 0 | 0.34 |
| Karina Krasnoyaruzhskaya | 3 | 0 | 0.34 |
| Sergey Galagan | 4 | 0 | 0.34 |