Paper Info
Title
FPGA parallel-pipelined AES-GCM core for 100G Ethernet applications
Abstract
The forthcoming IEEE 802.3ba Ethernet standard will provide data transmission at a bandwidth of 100 Gbit/s. Currently, the fastest cryptographic primitive approved by the U.S. National Institute for Standard and Technology, that combines data encryption and authentication, is the Galois/Counter Mode (GCM) of operation. If the feasibility to increase the speed of the GCM up to 100 Gbit/s on ASIC technologies has already been demonstrated, the FPGA implementation of the GCM in secure 100G Ethernet network systems arises some important structural issues. In this paper, we report on an efficient FPGA architecture of the GCM combined with the AES block cipher. With the parallelization of four pipelined AES-GCM cores we were able to reach the speed required by the new Ethernet standard. Furthermore, the time-critical binary field multiplication of the authentication process relies on four pipelined 2-step Karatsuba-Ofman multipliers.
Year
DOI
Venue
2010
10.1109/ESSCIRC.2010.5619894
Seville
Keywords
DocType
ISSN
cryptography,field programmable gate arrays,local area networks,100g ethernet applications,aes block cipher,asic technologies,fpga implementation,fpga parallel-pipelined aes-gcm core,galois/counter mode,ieee 802.3ba ethernet standard,authentication,cryptographic primitive,data encryption,pipelined 2-step karatsuba-ofman multipliers,time-critical binary field multiplication,galois counter mode,data transmission,radiation detectors,computer architecture,block cipher,encryption
Conference
1930-8833
ISBN
Citations 
PageRank 
978-1-4244-6662-7
22
1.46
References 
Authors
7
2
Name
Order
Citations
PageRank
Henzen, L.1221.46
Fichtner, Wolfgang2221.80