Name
Abstract | ||
|---|---|---|
This paper addresses complexity issues at algorithmic and architectural level of digital baseband receiver ASIC design for GSM/GPRS/EDGE, in order to reduce power and die area as desired for cellular applications. A 2.5G multi-mode architecture is implemented in 0.13 μm CMOS technology occupying 1.0 mm2 and dissipating only 1.3 mW in fastest EDGE data transmission mode. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/VLSISOC.2010.5642592 | VLSI System Chip Conference |
Keywords | DocType | ISBN |
3G mobile communication,CMOS digital integrated circuits,application specific integrated circuits,cellular radio,radio receivers,CMOS technology,EDGE data transmission mode,GSM-GPRS-EDGE,digital baseband receiver ASIC,power 1.3 mW,size 0.13 mum,2.5G,2G,Baseband,EDGE,EGPRS,Equalizer,GSM,Low Power,Mobile Communication,Receiver | Conference | 978-1-4244-6469-2 |
Citations | PageRank | References |
1 | 0.37 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christian Benkeser | 1 | 1 | 0.37 |
| Andreas Bubenhofer | 2 | 5 | 0.99 |
| Quiting Huang | 3 | 6 | 1.14 |