Paper Info
Title
Evaluating architecture and compiler design through static loop analysis
Abstract
Using the MAQAO loop static analyzer, we characterize a corpus of binary loops extracted from common benchmark suits such as SPEC, NAS, etc. and several industrial applications. For each loop, MAQAO extracts low-level assembly features such as: integer and floating-point vectorization ratio, number of registers used and spill-fill, number of concurrent memory streams accessed, etc. The distributions of these features on a large representative code corpus can be used to evaluate compilers and architectures and tune them for the most frequently used assembly patterns. In this paper, we present the MAQAO loop analyzer and a characterization of the 4857 binary loops. We evaluate register allocation and vectorization on two compilers and propose a method to tune loop buffer size and stream prefetcher based on static analysis of benchmarks.
Year
DOI
Venue
2013
10.1109/HPCSim.2013.6641465
High Performance Computing and Simulation
Keywords
Field
DocType
feature extraction,optimising compilers,program control structures,program diagnostics,software architecture,storage management,MAQAO loop static analyzer,architecture design evaluation,assembly patterns,benchmark suits,binary loops,compiler design evaluation,large representative code corpus,loop buffer size,low-level assembly feature extraction,prefetcher,register allocation evaluation,static loop analysis,vectorization evaluation,Benchmarking and Assessment,HPC Monitoring and Instrumentation,Modeling,Simulation and Evaluation Techniques,Software Monitoring and Measurement
Register allocation,Foreach loop,Computer science,Parallel computing,Static analysis,Vectorization (mathematics),Compiler,Loop interchange,Compiler construction,Spec#
Conference
ISBN
Citations 
PageRank 
978-1-4799-0836-3
8
0.66
References 
Authors
8
4
Name
Order
Citations
PageRank
Yuriy Kashnikov180.66
Pablo de Oliveira Castro280.66
Emmanuel Oseret380.66
William Jalby481.00