Name
Title | ||
|---|---|---|
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip |
Abstract | ||
|---|---|---|
Through silicon vias (TSVs) provide an efficient way to support vertical communication among different layers of a vertically stacked chip, enabling scalable 3-D networks-on-chip (NoC) architectures. Unfortunately, low TSV yields significantly impact the feasibility of high-bandwidth vertical connectivity. In this paper, we present a semi-automated design flow for 3-D NoCs including a defect-tolerance scheme to increase the global yield of 3-D stacked chips. Starting from an accurate physical and geometrical model of TSVs: 1) we extract a circuit-level model for vertical interconnections; 2) we use it to evaluate the design implications of extending switch architectures with ports in the vertical direction; moreover, 3) we present a defect-tolerance technique for TSV-based multi-bit links through an effective use of redundancy; and finally, 4) we present a design flow allowing for post-layout simulation of NoCs with links in all three physical dimensions. Experimental results show that a 3-D NoC implementation yields around 10% frequency improvement over a 2-D one, thanks to the propagation delay advantage of TSVs and the shorter links. In addition, the adopted fault tolerance scheme demonstrates a significant yield improvement, ranging from 66% to 98%, with a low area cost (20.9% on a vertical link in a NoC switch, which leads a modest 2.1% increase in the total switch area) in 130 nm technology, with minimal impact on very large-scale integrated design and test flows. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/TCAD.2010.2065990 | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions |
Keywords | DocType | Volume |
VLSI,electronic design automation,fault tolerance,integrated circuit interconnections,integrated circuit layout,integrated circuit modelling,integrated circuit testing,network-on-chip,redundancy,switching circuits,three-dimensional integrated circuits,3D networks-on-chip,TSV-based multibit links,VLSI test flow,circuit-level model,defect-tolerance scheme,defect-tolerance technique,fault-tolerant vertical links,geometrical model,global yield,high-bandwidth vertical connectivity,physical model,post-layout simulation,propagation delay,redundancy,scalable 3D NoC architecture,semiautomated design flow,switch architectures,through silicon vias,vertical communication,vertical interconnections,vertically stacked chip,very large-scale integrated design flow,3-D integration,fault tolerance,network-on-chip (NoC) | Journal | 30 |
Issue | ISSN | Citations |
1 | 0278-0070 | 42 |
PageRank | References | Authors |
1.48 | 13 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Igor Loi | 1 | 62 | 2.42 |
| Angiolini, F. | 2 | 43 | 1.83 |
| Fujita, Shinobu | 3 | 46 | 2.35 |
| Subhasish Mitra | 4 | 3657 | 228.90 |