Name
Abstract | ||
|---|---|---|
3T1D-DRAM cells will still be operative with 7nm FinFETs but their performance is significantly degraded when factoring in variability. In order to improve the cell robustness against device process variation and high environment temperatures, we propose a Dual-VT strategy. Our results show a larger retention time, significant cell spread reduction and reliable behavior up to 100°C. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/MWSCAS.2013.6674590 | Circuits and Systems |
Keywords | Field | DocType |
dram chips,mosfet,finfet 3t1d-dram cells,cell robustness,cell spread reduction,device process variation,dual-vt strategy,environment temperatures,retention time,size 7 nm,variability robustness enhancement | Dram,Computer science,Robustness (computer science),Electronic engineering,Process variation,MOSFET,Factoring | Conference |
ISSN | Citations | PageRank |
1548-3746 | 0 | 0.34 |
References | Authors | |
6 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| E. Amat | 1 | 30 | 10.36 |
| C. G. Almudéver | 2 | 1 | 1.04 |
| nivard aymerich | 3 | 0 | 0.34 |
| antonio rubio | 4 | 0 | 0.34 |
| R. Canal | 5 | 14 | 2.26 |