Name
Abstract | ||
|---|---|---|
To meet energy-efficient performance demands, the computing industry has moved to parallel computer architectures, such as chip-multi-processors (CMPs), internally interconnected via networks-on-chip (NoC) to meet growing communication needs. Achieving scaling performance as core counts increase to the hundreds in future CMPs, however, will require high performance, yet energy-efficient interconnects. Silicon nanophotonics is a promising replacement for electronic on-chip interconnect due to its high bandwidth and low latency, however, prior techniques have required high static power for the laser and ring thermal tuning. We propose a novel nanophotonic NoC architecture, LumiNOC, optimized for high performance and power-efficiency. This paper makes three primary contributions: a novel, nanophotonic architecture which partitions the network in to subnets for better efficiency; a purely photonic, in-band, distributed arbitration scheme; and a channel sharing arrangement utilizing the same waveguides and wavelengths for arbitration as data transmission. In a 64-node NoC under synthetic traffic, LumiNOC enjoys 50% lower latency at low loads and ~40% higher throughput per Watt on synthetic traffic, versus other reported photonic NoCs. LumiNOC reduces latencies ~40% versus an electrical 2D mesh NoCs on the PARSEC shared-memory, multithreaded benchmark suite. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/SLIP.2013.6681679 | System Level Interconnect Prediction |
Keywords | Field | DocType |
elemental semiconductors,multi-threading,nanophotonics,network-on-chip,parallel architectures,shared memory systems,silicon,CMP,LumiNOC,PARSEC shared-memory,Si,channel sharing arrangement,chip-multiprocessors,computing industry,core counts,data transmission,distributed arbitration scheme,electrical 2D mesh NoC,electronic on-chip interconnect,energy-efficient interconnects,laser tuning,multithreaded benchmark suite,nanophotonic architecture,parallel computer architectures,photonic network-on-chip,power-efficiency,ring thermal tuning,scaling performance,synthetic traffic,CMP,NoC,Power Efficiency,Synthetic/Realistic Workload | Parsec,Data transmission,Latency (engineering),Computer science,Network on a chip,Communication channel,Electronic engineering,Latency (engineering),Throughput,Interconnection,Embedded system | Conference |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mark Browning | 1 | 0 | 0.34 |
| Cheng Li | 2 | 0 | 0.34 |
| Paul V. Gratz | 3 | 18 | 3.46 |
| Samuel Palermo | 4 | 0 | 1.01 |