Title
A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses
Abstract
This article presents a reconfigurable hardware/software architecture for binary acceleration of embedded applications. A Reconfigurable Processing Unit (RPU) is used as a coprocessor of the General Purpose Processor (GPP) to accelerate the execution of repetitive instruction sequences called Megablocks. A toolchain detects Megablocks from instruction traces and generates customized RPU implementations. The implementation of Megablocks with memory accesses uses a memory-sharing mechanism to support concurrent accesses to the entire address space of the GPP’s data memory. The scheduling of load/store operations and memory access handling have been optimized to minimize the latency introduced by memory accesses. The system is able to dynamically switch the execution between the GPP and the RPU when executing the original binaries of the input application. Our proof-of-concept prototype achieved geometric mean speedups of 1.60× and 1.18× for, respectively, a set of 37 benchmarks and a subset considering the 9 most complex benchmarks. With respect to a previous version of our approach, we achieved geometric mean speedup improvements from 1.22 to 1.53 for the 10 benchmarks previously used.
Year
DOI
Venue
2015
10.1145/2629468
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Keywords
Field
DocType
design,experimentation,fpga,hardware acceleration,hardware/software architectures,instruction trace,megablock,memory access,microblaze,performance,reconfigurable processor,special-purpose and application-based systems
MicroBlaze,Address space,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Hardware acceleration,Coprocessor,Toolchain,Embedded system,Speedup,Reconfigurable computing
Journal
Volume
Issue
ISSN
7
4
1936-7406
Citations 
PageRank 
References 
2
0.38
16
Authors
3
Name
Order
Citations
PageRank
Nuno Paulino1286.24
João Canas Ferreira27216.69
João M. P. Cardoso346257.24