Name
Abstract | ||
|---|---|---|
This paper presents a simple architecture for clock-fault detection in high-speed applications. The overall principle consists in converting a possible error of time to a logic voltage level. When a high voltage level is present at the output, a reliable clock is detected whereas a low voltage level implies a clock error. This detection system is intended for all System-on-Chip such as microcontrollers which use external clock from 4 MHz to 50 MHz. The proposed circuit is realized in CMOS 40 nm process technology. Simulation results prove the suitability of the structure and its integration on silicon is strongly considered by clock error detection in integrated circuits. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/MIPRO.2015.7160524 | Information and Communication Technology, Electronics and Microelectronics |
Keywords | Field | DocType |
Clock error,Clock-fault detection,Crystal oscillator,High-Speed Circuits,Peak detector | Clock signal,Clock gating,Computer science,Clock domain crossing,Computer network,Electronic engineering,Synchronous circuit,Clock skew,Digital clock manager,CPU multiplier,Clock rate,Embedded system | Conference |
Citations | PageRank | References |
2 | 0.39 | 2 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Amaud Gamet | 1 | 2 | 0.72 |
| Bacher, Y. | 2 | 2 | 0.39 |
| Stéphane Meillére | 3 | 12 | 4.05 |
| Le Fevre, P. | 4 | 2 | 0.39 |
| Philippe Le Fevre | 5 | 2 | 0.72 |
| Nicolas Froidevaux | 6 | 2 | 0.72 |