Name
Abstract | ||
|---|---|---|
To improve the stack yield of channel-based 3D DRAM, we propose two 3D redundancy schemes, i.e., Configu-rable Cubical Redundancy Architecture 1 and 2 (CoCRA1 and CoCRA2). There are three features of the CoCRAs, i.e., 1) the spares can be shared across dies, 2) the spare memory is configu-rable to allow efficient repair of row, column, and cluster failures, and 3) the spare design reduces die matching constraints for higher stack yield. In CoCRA1, the global spares that can be shared across dies are associated with each DRAM die as conven-tional DRAMs. We propose a word-based redundancy analysis (RA) algorithm to enable spare sharing. In CoCRA2, we use an SRAM on the logic die as global spares, which have higher flexi-bility than CoCRA1. The experimental result shows that CoCRA1 can achieve 28.09% higher stack yield than the tradi-tional redundancy architecture, with only 50% of its spare space. There is only 0.05% and 0.2% area overhead on the logic die and DRAM die, respectively. On the other hand, CoCRA2 can fur-ther improve the stack yield to almost 100%, but with 2.3 times higher area overhead than CoCRA1. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/MDAT.2015.2455347 | Design & Test, IEEE |
Keywords | Field | DocType |
3D DRAM,built-in self-repair (BISR),built-in self-test (BIST),memory testing,redundancy analysis (RA),redundancy repair,yield improvement | Dram,Registered memory,Interleaved memory,Algorithm design,Computer science,Parallel computing,Communication channel,Electronic engineering,Redundancy (engineering),Memory rank,Built-in self-test | Journal |
Volume | Issue | ISSN |
PP | 99 | 2168-2356 |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lin, B. | 1 | 0 | 0.34 |
| Chiang, W. | 2 | 0 | 0.34 |
| Muh-Cherng Wu | 3 | 227 | 16.58 |
| Min-Young Lee | 4 | 33 | 23.26 |