Paper Info
Title
Identification of high power consuming areas with gate type and logic level information
Abstract
Power-related problems in at-speed scan testing have become more and more serious, since excessive IR-drop caused by excessive power consumption results in overtesting. There are two important factors in low-power testing: one is power estimation, the other is power reduction. Several estimation methods have been proposed based on the analysis of switching activity characteristics. In order to estimate the impact of IR-drop, it is more important to consider the area containing many cells which consume excessive power than to consider the total number of switching activity in a circuit. In this paper, we propose a novel method for identifying areas where excessive IR-drop likely occurs without using test vectors. Visualized experimental results for IWLS 2005 benchmark circuits demonstrate that the proposed method can effectively identify areas containing many cells which consume higher power than others. Such areas identified can be used in low-power test generation so as to achieve effective and efficient results.
Year
DOI
Venue
2015
10.1109/ETS.2015.7138773
European Test Symposium
Keywords
Field
DocType
integrated logic circuits,logic testing,low-power electronics,at-speed scan testing,gate type information,high power consuming area identification,logic level information,power estimation,power reduction,switching activity,voltage drop,layout design,low-power testing,power estimation,test generation
Logic gate,Pass transistor logic,Computer science,Real-time computing,Electronic engineering,Power demand,Logic family,Electronic circuit,AND gate,Common Power Format,Power consumption
Conference
Citations 
PageRank 
References 
6
0.47
11
Authors
4
Name
Order
Citations
PageRank
K. Miyase11166.12
Matthias Sauer219520.02
B. Becker319121.44
Wen, X.460.47