Paper Info
Title
BER-based wear leveling and bad block management for NAND flash
Abstract
One of the main challenges keeping flash memories from achieving widespread distribution is their limited endurance. The programming and erasing from re-writes damages the cells, progressively increasing the number of errors until information can no longer be stored reliably. Most manufacturers employ powerful ECC techniques, but there is a limit to the number of errors that these can correct. When the number of errors goes beyond the capability of the ECC, it is necessary to invoke RAID, which introduces significant latency and jeopardizes the speed of the memory if used too often. This paper introduces a method for estimating the BER that a flash page will exhibit after retention and uses this estimate for wear leveling. Instead of leveling out the number of PE cycles in all the blocks, the proposed scheme attempts to wear all the blocks evenly so that they all suffer the same BER. Additionally, the estimate will be used to detect bad blocks, those likely to exhibit a number of errors beyond the ECC correction capability, and retire them from further use.
Year
DOI
Venue
2015
10.1109/ICC.2015.7248337
IEEE International Conference on Communications
Keywords
Field
DocType
NAND circuits,RAID,error correction codes,error statistics,flash memories,wear,BER-based wear leveling,ECC correction capability techniques,NAND flash memories,PE cycles,RAID,bad block detection,bad block management,bit error rate,error correcting codes,flash page
Wear leveling,Latency (engineering),Computer science,NAND gate,Real-time computing,RAID,Computer hardware
Conference
ISSN
Citations 
PageRank 
1550-3607
1
0.36
References 
Authors
7
4
Name
Order
Citations
PageRank
Borja Peleato14095142.71
Haleh Tabrizi2273.68
Rajiv Agarwal3476.34
Jeffrey Ferreira410.36